IEC 63093-9:2020

Ferrite cores - Guidelines on dimensions and the limits of surface irregularities - Part 9: Planar cores

IEC 63093-9:2020

Name:IEC 63093-9:2020   Standard name:Ferrite cores - Guidelines on dimensions and the limits of surface irregularities - Part 9: Planar cores
Standard number:IEC 63093-9:2020   language:English and French language
Release Date:15-Apr-2020   technical committee:TC 51 - Magnetic components, ferrite and magnetic powder materials
Drafting committee:WG 1 - TC 51/WG 1   ICS number:01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION

IEC 63093-9
Edition 1.0 2020-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Ferrite cores – Guidelines on dimensions and the limits of
surface irregularities –
Part 9: Planar-cores
Noyaux ferrites – Lignes directrices relatives aux dimensions
et aux limites des irrégularités de surface –
Partie 9: Noyaux planaires




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IEC 63093-9
Edition 1.0 2020-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Ferrite cores – Guidelines on dimensions and the limits of

surface irregularities –
Part 9: Planar-cores
Noyaux ferrites – Lignes directrices relatives aux dimensions

et aux limites des irrégularités de surface –

Partie 9: Noyaux planaires
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 29.100.10 ISBN 978-2-8322-8080-5

– 2 – IEC 63093-9:2020 © IEC 2020
CONTENTS
FOREWORD . 4
INTRODUCTION . 6
1 Scope . 7
2 Normative references . 7
3 Terms and definitions . 7
4 Primary dimensions . 7
4.1 Planar shapes and dimensions . 7
4.2 Dimensions and effective parameters of planar EL-core and mating PLT-core . 8
4.3 Dimensions and effective parameters of low-profile E-core and mating PLT-
core . 10
4.4 Dimensions and effective parameters of low-profile ER-core and mating
PLT-core . 12
5 Limits of surface irregularities . 15
5.1 General . 15
5.2 Examples of surface irregularities . 16
5.3 Chips and ragged edges . 17
5.3.1 General . 17
5.3.2 Chips and ragged edges on the mating surfaces . 17
5.3.3 Chips and ragged edges on other surfaces . 18
5.4 Cracks . 20
5.5 Flash . 20
5.6 Pull-outs . 20
5.7 Crystallites . 24
5.8 Pores . 24
Annex A (normative) Low-profile core design . 26
A.1 General design . 26
A.2 EL-core design . 26
A.3 ER-core design . 27
Annex B (informative) Reference values of allowable areas of chips . 29
Bibliography . 31

Figure 1 – Planar EL-core and mating PLT-core. 8
Figure 2 – Low-profile E-core and mating PLT-core . 10
Figure 3 – Low-profile ER-core and mating PLT-core . 12
Figure 4 – Examples of surface irregularities for planar EL-core . 16
Figure 5 – Examples of surface irregularities for low-profile E-core . 16
Figure 6 – Examples of surface irregularities for low-profile ER-core. 16
Figure 7 – Chip location for planar EL-core . 17
Figure 8 – Chip location for low-profile E-core . 17
Figure 9 – Chip location for low-profile ER-core . 17
Figure 10 – Cracks and pull-out location for planar EL-core . 20
Figure 11 – Cracks and pull-out location for low-profile E-core . 21
Figure 12 – Cracks and pull-out location for low-profile ER-core . 21
Figure 13 – Reference dimensions for EL-core . 21

Figure 14 – Reference dimensions for E-core . 22
Figure 15 – Reference dimensions for ER-core . 23
Figure 16 – Example of the location of a crystallite on planar EL-core . 24
Figure 17 – Example of the location of a crystallite on low-profile E-core . 24
Figure 18 – Example of the location of a crystallite on low-profile ER-core . 24
Figure 19 – Example of the location of a pore on planar EL-core . 25
Figure 20 – Example of the location of a pore on low-profile E-core . 25
Figure 21 – Example of the location of a pore on low-profile ER-core . 25

Table 1 – Dimensions of planar EL-core EL and mating PLT-core . 9
Table 2 – Effective parameter values and A values . 10
min
Table 3 – Dimensions of low-profile E-core and mating PLT-core . 11
Table 4 – Effective parameter values and A values . 12
min
Table 5 – Dimensions of low-profile ER-core and mating PLT-core . 13
Table 6 – Effective parameter values and A values . 14
min
Table 7 – Area and length reference for visual inspection . 19
Table 8 – Limits of cracks for planar EL-core . 22
Table 9 – Limits of cracks for low-profile E-core . 23
Table 10 – Limits of cracks for low-profile ER-core . 23
Table A.1 – Sizes and design ratios for ER-core . 28
Table B.1 – Allowable areas of chips for planar EL-core . 29
Table B.2 – Allowable areas of chips for low-profile E-core . 29
Table B.3 – Allowable areas of chips for low-profile ER-core. 30

– 4 – IEC 63093-9:2020 © IEC 2020
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
FERRITE CORES – GUIDELINES ON DIMENSIONS AND
THE LIMITS OF SURFACE IRREGULARITIES –

Part 9: Planar-cores
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
Publication(s)”). Their preparation is entrusted to technical committees; any IEC Natio
...

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