IEC 62026-2:2008

Low-voltage switchgear and controlgear - Controller-device interfaces (CDIs) - Part 2: Actuator sensor interface (AS-i)

IEC 62026-2:2008

Name:IEC 62026-2:2008   Standard name:Low-voltage switchgear and controlgear - Controller-device interfaces (CDIs) - Part 2: Actuator sensor interface (AS-i)
Standard number:IEC 62026-2:2008   language:English language
Release Date:09-Jul-2019   technical committee:SC 121A - Low-voltage switchgear and controlgear
Drafting committee:WG 3 - TC 121/SC 121A/WG 3   ICS number:01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION

IEC 62026-2
Edition 2.0 2008-01
INTERNATIONAL
STANDARD
Low-voltage switchgear and controlgear – Controller-device interfaces (CDIs) –
Part 2: Actuator sensor interface (AS-i)



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IEC 62026-2
Edition 2.0 2008-01
INTERNATIONAL
STANDARD
Low-voltage switchgear and controlgear – Controller-device interfaces (CDIs) –
Part 2: Actuator sensor interface (AS-i)

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
XH
ICS 29.130.20 ISBN 2-8318-9512-X

– 2 – 62026-2 © IEC:2008(E)
CONTENTS
FOREWORD.7

1 Scope and object.9
2 Normative references.9
3 Terms, definitions, symbols and abbreviations.11
4 Classification.18
4.1 Overview.18
4.2 Components and interfaces .19
5 Characteristics.21
5.1 Overview.21
5.2 Signal characteristics .21
5.3 Power and data distribution .23
5.4 AS-i topology and other components .25
5.5 Communication.27
5.6 AS-i single transactions.30
5.7 AS-i combined transactions .42
5.8 AS-i error detection .59
6 Product information .60
6.1 Instructions for installation, operation and maintenance .60
6.2 Profiles.60
6.3 Marking.61
7 Normal service, mounting and transport conditions.62
7.1 Normal service conditions .62
7.2 Conditions during transport and storage .62
7.3 Mounting.63
8 Constructional and performance requirements.63
8.1 AS-i transmission medium.63
8.2 AS-i power supply.66
8.3 AS-i repeater and other components .68
8.4 AS-i slave.69
8.5 AS-i master.85
8.6 Electromagnetic compatibility (EMC) .89
9 Tests.90
9.1 Kinds of tests.90
9.2 Test of transmission medium .91
9.3 Test of the AS-i power supply.92
9.4 Test of an AS-i repeater and other components.98
9.5 Test of an AS-i slave .106
9.6 Test of a AS-i master.120

Annex A (normative) Slave profiles .135
Annex B (normative) Master profiles .213

Figure 1 − AS-i components and interfaces.19
Figure 2 − Transmission coding .21

62026-2 © IEC:2008(E) – 3 –
Figure 3 − Receiver requirements .23
Figure 4 − AS-i power supply .24
Figure 5 − Equivalent schematic of symmetrization and decoupling circuit .25
Figure 6 − Model of the AS-i transmission medium.26
Figure 7 − Transactions .28
Figure 8 − Master and slave pause as viewed from master/slave point of view.28
Figure 9 − Representation of the master pause.29
Figure 10 − Structure of a master request .31
Figure 11 − Structure of a slave response.34
Figure 12 − Structure of a data exchange request (top: standard address mode;
bottom: extended address mode) .34
Figure 13 − Structure of the slave response (Data_Exchange) .35
Figure 14 − Structure of the Write_Parameter request (top: standard addressing mode;
bottom: extended addressing mode) .35
Figure 15 − Structure of the slave response (Write_Parameter) .35
Figure 16 − Structure of the Address_Assignment request .36
Figure 17 − Structure of the slave response (Address_Assignment).36
Figure 18 − Structure of the Write_Extended_ID-Code_1 request .36
Figure 19 − Structure of the slave response (Write_Extended_ID-Code_1) .36
Figure 20 − Structure of the Reset_Slave request (top: standard addressing mode;
bottom: extended addressing mode) .37
Figure 21 − Structure of the slave response (Reset_Slave).37
Figure 22 − Structure of the Delete_Address request (top: standard addressing mode;
bottom: extended addressing mode) .37
Figure 23 − Structure of the slave response (Delete_Address).37
Figure 24 – Structure of the Read_I/O_Configuration request top: standard addressing
mode; bottom: extended addressing mode).38
Figure 25 – Structure of the slave response (Read_I/O_Configuration) .38
Figure 26 – Structure of Read_Identification_Code request (top: standard addressing
mode; bottom: extended addressing mode).39
Figure 27 – Structure of the slave response (Read_Identification_Code) .39
Figure 28 – Structure of Read_Extended_ID-Code_1/2 Request (top: standard
addressing mode; bottom: extended addressing mode).
Figure 29 – Structure of the slave response Read_Extended_ID-Code_1/2.40
Figure 30 − Structure of Read_Status request (top: standard addressing mode;
bottom: extended addressing mode) .41
Figure 31 − Structure of the slave response (Read_Status) .41
Figure 32 − Structure of R1 request (top: standard addressing mode; bottom:
extended addressing mode).41
Figure 33 − Structure of the slave response (R1) .41
Figure 34 – Structure of the Broadcast (Reset) request.42
Figure 35 – Definition of the I/O data bits in combined transaction type 1 .43
Figure 36 – Definition of the parameter bits in combined transaction type 1 .43
Figure 37 – Function sequence to Read ID, Read Diagnosis, Read Parameter in
combined transaction type 1 .

– 4 – 62026-2 © IEC:2008(E)
Figure 38 – Function sequence to Write Parameter in combined transaction type 1 .47
Figure 39 – Behaviour of the slave receiving a complete parameter string from the
master in combined transaction type 1.48
Figure 40 – Definition of the I/O data bits in combined transaction type 2 .49
Figure 41 – Typical combined transaction type 2 signals as viewed by an oscilloscope
(both data channels run idle) .50
Figure 42 – Typical combined transaction type 2 signals (the master transmits the byte
10101011 , the slave transmits 01110101 ):.51
Bin Bin
Figure 43 – Definition of the I/O data bits in combined transaction type 3 (4I/4O) .52
Figure 44 – Definition and state diagram of the slave for combined transaction type 3 .53
Figure 45 – Definition of the I/O data bits in combined transaction type 4 .55
Figure 46– AS-i standard cable for field installation .63
Figure 47 − AS-i cabinet cable .64
Figure 48 – Equivalent schematic of decoupling circuit .68
Figure 49 – Decoupling circuit using a transformer .68
Figure 50 – Typical timing diagram for bidirectional input/outputs (D1, . D3 = voltage
level at respective data port).
Figure 51 – Main state diagram of an AS-i slave .
...

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